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[SCM] oc8051

Description: 51的VERILOG代码！适用于Xilinx的FPGA-51 VERILOG code! In Xilinx FPGA
Platform: | Size: 1220608 | Author: 林建加 | Hits:

[VHDL-FPGA-Verilog] DSPBuilderFIR.files

Description: 在信息信号处理过程中，如对信号的过滤、检测、预测等，都要使用滤波器，数字滤波器是数字信号处理（DSP，DigitalSignalProcessing）中使用最广泛的一种器件。常用的滤波器有无限长单位脉冲响应（ⅡR）滤波器和有限长单位脉冲响应（FIR）滤波器两种[1]，其中，FIR滤波器能提供理想的线性相位响应，在整个频带上获得常数群时延从而得到零失真输出信号，同时它可以采用十分简单的算法实现，这两个优点使FIR滤波器成为明智的设计工程师的首选，在采用VHDL或VerilogHDL等硬件描述语言设计数字滤波器时，由于程序的编写往往不能达到良好优化而使滤波器性能表现一般。而采用调试好的IPCore需要向Altera公司购买。笔者采用了一种基于DSPBuilder的FPGA设计方法，使FIR滤波器设计较为简单易行，并能满足设计要求。-err
Platform: | Size: 96256 | Author: yaoming | Hits:

[Other Embeded program] 01_GettingStarted

Description: This getting started exercise will guide you through the step-by-step process of transforming a MATLAB floating-point model into a hardware module that can be implemented in silicon (FPGA or ASIC). The design is a general purpose FIR filter taken from the AccelDSP Examples directory.-This exercise will guide y ou through the step-by-step process of transfo rming a MATLAB floating-point model into a hard ware module that can be implemented in silicon ( FPGA or ASIC). The design is a general purpose FI R filter taken from the AccelDSP Examples direc tory.
Platform: | Size: 5120 | Author: 杨平 | Hits:

[Other] Farsight060724FPGA-2

Description: EDA\FPGA设计入门\Farsight060724FPGA-2.rar 这个东西对初学EDA设计的人很有用-EDA \ FPGA design entry \ Farsight060724FPGA- 2.ra r this thing right novice EDA design of useful
Platform: | Size: 3137536 | Author: 罗伶俐 | Hits:

[VHDL-FPGA-Verilog] baseball

Description: 用VHDL开发的棒球游戏，可以在QuartusII环境下编译，适用于各种FPGA开发板。-VHDL development of the baseball game, in QuartusII environment compiler, apply to all FPGA development board.
Platform: | Size: 56320 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] TestUSB

Description: fpga之ep1 c6的usb实验源码,经实验验证好好用,大家可以试试看哦-FPGA ep1c6 of the usb-source experiment, the experimental validation properly used, we can give it a try Oh
Platform: | Size: 157696 | Author: liuheng | Hits:

[VHDL-FPGA-Verilog] BasicRSA

Description: RSA加密算法的VHDL实现，通过实际FPGA验证。-RSA encryption algorithm of VHDL realize, through actual FPGA verification.
Platform: | Size: 9216 | Author: 张开文 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
Platform: | Size: 651264 | Author: jimmy | Hits:

[VHDL-FPGA-Verilog] fpgaandmcuand25h20

Description: FPGA 和ＭＣＵ的并口通信　及ＭＣＵ和Ｅ２ＰＲＯＭ(FM25H20)SPI通信　　　 功能：ＦＰＧＡ对ＭＣＵ的写（ＦＰＧＡ发给ＭＣＵ的地址是写进Ｅ２ＰＲＯＭ的地址　，Ｅ２ＰＲＯＭ中的数据是　　　　　　ＦＰＧＡ发送的数据。） 　　　　ＦＰＧＡ对ＭＣＵ的读（ＦＰＧＡ读取它发给ＭＣＵ在Ｅ２ＰＲＯＭ中存取的数据） 　　　　程序和图见附件　　　恳请高手指导　　小弟急啊！-FPGA and MCU
Platform: | Size: 34816 | Author: 爱迪生法 | Hits:

[VHDL-FPGA-Verilog] R

Description: 双向移位寄存器的原理设计程序，对于初学者将会有很大帮助，尤其在设计功能比较复杂的FPGA时，有些问题其实用这个就很简单-The principle of bi-directional shift register the design process, for beginners there will be a great help, especially in the design features of the FPGA more complex, there are some problems with this very simple
Platform: | Size: 2048 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] Design_of_Traffic_Light_Controller_Based_on_VHDL.r

Description: :传统的交通灯控制器多数由单片机或PLC来实现,文中介绍了基于VHDL硬件描述语言进行交通灯控制 器设计的一般思路和方法。选择XIL INX公司低功耗、低成本、高性能的FPGA芯片,采用ISE5. X和MODELSIM SE 6. 0开发工具进行了程序的编译和功能仿真。最后给出了交通灯控制器的部分VHDL源程序和仿真结果,仿 真结果表明该系统的设计方案正确。-Traffic light controller is usually developed bymicro p rocessor or PLC. This paper introduces the gen2 eral design methods of traffic light controller base on VHDL ( hardware descrip tion language). the FPGA chip of XIL2 INX Corporation was chosen with the low power loss, the low cost and the high performance, the XIL INX ISE5. X andMODELSIM 6. 0 development toolswas used to comp ile and stimulate. Finally, The VHDL source p rogrammer and simulating results of traffic light controller are given. The simulating results show that the design method is cor2 rect
Platform: | Size: 434176 | Author: li | Hits:

[Program doc] Dual_port_RAM

Description: 很精彩的双端口RAM应用笔记，对搞单片机、FPGA的都有帮助。-dual_port_ram
Platform: | Size: 644096 | Author: chenlei | Hits:

[VHDL-FPGA-Verilog] groundmotionsignalacquisitionandprocessingsystem.r

Description: 基于FPGA与PC机的地震动信号采集与处理系统的研究与实现-FPGA and PC-based machine ground motion signal acquisition and processing system research and implementation
Platform: | Size: 3678208 | Author: wlf | Hits:

[VHDL-FPGA-Verilog] tut_nios2_introduction

Description: This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.
Platform: | Size: 116736 | Author: *Roma* | Hits:

[VHDL-FPGA-Verilog] FPGA-basedhardwareimplementationofneuralnetworks.r

Description: 基于FPGA的神经网络硬件实现中的关键问题研究，适合用fpga研究神经网络的工程人员参考-FPGA-based hardware implementation of neural networks in the study of key issues for research with neural networks fpga reference works
Platform: | Size: 88064 | Author: bonjour | Hits:

[Software Engineering] FPGA

Description: 针对MT9M111数字图像传感器,采用Cyclone系列 EP1C6Q240C6作为主控芯片,设计并实现了ITU-R BT.656视频数据的采集、色彩空间转换、DVI-I显示控制的数字视频转换系统。系统可以将传感器的输入图像以1280×960(60Hz)和 1280×1024(60Hz)格式输出到DVI-I显示器上,并具有图像静止功能,同时在系统空闲时,可以将系统设置为待机状态,来降低功耗。-Aimed at the digital image sensor MT9M111,used Cyclone EP1C6Q240C6 as the main control chip,designed and implemented the conversion system of the collection of the ITU-R BT.656 video data,color space conversion,and the display on DVI-I monitor.This system can display the image from the sensor on DVI-I monitor in the mode of 1280960(60 Hz)or 12801024(60 Hz),image freezing is also supported.Moreover,the system can be set into standby state when the system is idled,for low power consumption.
Platform: | Size: 563200 | Author: 将建 | Hits:

[VHDL-FPGA-Verilog] FPGA(DDS)

Description: 采用FPGA来实现DDS，发出任意频率的三角波，方波或正弦波-Use FPGA to implement DDS, given any frequency triangle wave, square wave or sine wave
Platform: | Size: 416768 | Author: haha | Hits:

[VHDL-FPGA-Verilog] ThedesignofLDPCEncodeasedonFieldProgrammGateArry.r

Description: In this paper, we introduce the priplince of the LDPC Encode. And introduce how to realize the LDPC encode based on the FPGA.-The design of LDPC Encode based on Field Programm Gate Arry
Platform: | Size: 612352 | Author: SEU | Hits:

[VHDL-FPGA-Verilog] 3813412-Matlab-Simulink-Simulink-Matlab-to-Vhdl.r

Description: Simulink/Matlab-to-VHDL Route for Full-Custom/FPGA Rapid Prototyping of DSP Algorithms
Platform: | Size: 147456 | Author: T. H. Sutikno | Hits:

[VHDL-FPGA-Verilog] FPGA黑金开发板AX301原理图

Description: 掌 握 V e r i l o g H D L 语 言 需 要 的 不 只 是 技 术 而已 ， 最 重 要 是 那 颗 安 静 的 心 ， 安 静 的 心 会 带 读 者 乘 风 破 浪 ， 一 方 通 行 。 此 外 记 录 笔 记 的习 惯 更 为 重 要 ， 向 自 己 学 习 比 起 向 他 人 学 习 更 有 学 习 的 价 值 。(It is not only the skill that is required to hold V e r I l o g H D l, but the most important thing is the quiet heart, the quiet heart will take the reader in the wind to break the waves, and the one side will pass.The habit of recording and recording is more important, and it is more valuable to learn from him than to learn from him.)
Platform: | Size: 117760 | Author: 你四哥 | Hits:
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